Various loads including output pads, off-chip loads, and measuring apparatuses, reaching about 50 pF in sum, are externally connected with a chip. So, a specially designed buffer, also called as output driver, instead of a conventional buffer is needed in order to drive these high loads.
FIG. 1 is a circuit diagram showing a data output buffer circuit according to the related art. FIG. 2 is a timing diagram which shows the data output pulses upon a Read command in a double data rate (DDR) synchronous dynamic random access memory (SDRAM) employing the output buffer of FIG. 1.
Referring to FIG. 1, the data output buffer circuit according to the related art includes: a latch 10 for holding ‘NETUP1’ and ‘NETDN1’, which are output data of data control circuits within a chip; a data out driver 30 for outputting amplified data; and a data out pre-driver 20 for driving the data out driver 30.
On the other hand, the ‘NETUP1’ and ‘NETDN1’ signals mentioned above can be viewed as pull-up and pull-down control signals respectively. ‘NETUP1’ and ‘NETUP2’ each other have different logic values owing to the inverter INV. ‘NETDN1’ and ‘NETDN2’ have the same logic values.
From now on, the behavior of the output buffer circuit having the structure mentioned above is explained with reference to FIG. 2.
As shown in FIG. 2, when a DRAM Read command is given with reference to an external clock input CLK, data are outputted through the data output buffer circuit after the CAS latency.
While the data are not outputted, the ‘NETUP2’ node maintains ‘logic high’ (hereinafter, referred to as H), the power source voltage level VDD, and also the ‘NETUP2’ node maintains ‘logic low’ (hereinafter, referred to as L), the ground voltage level VSS, so as to disable both a PMOS transistor 30a and an NMOS transistor 30a, and cause the output DQ to maintain high impedance state (hereinafter, referred to as Hi-Z). On this occasion, Hi-Z corresponds to the half of the power source voltage level, namely ‘VDD/2’ level. During this time, the data control circuits output logic L to both ‘NETUP1’ and ‘NETDN1’.
When the output DQ is desired to be logic H, the data control circuits set logic H and L to ‘NETUP1’ and ‘NETDN1’ respectively so as to set logic L to both ‘NETUP2’ and ‘NETDN2’. When the output DQ is desired to be logic L, the data control circuits set logic L and H to ‘NETUP1’ and ‘NETDN1’ respectively so as to set logic H to both ‘NETUP2’ and ‘NETDN2’.
On the other hand, as shown in FIG. 2, when data are outputted by a Read command, the first data output D0, starting from Hi-Z, is outputted earlier than the consecutive data outputs D1, D2, and D3. In particular, the fact that the first data output D0 is outputted early with reference to the external clock CLK can result in errors at high speed interfaces.
FIG. 3 is a timing diagram showing the AC timing of the Read operation of a DDR SDRAM employing the related art output buffer circuits.
Referring to FIG. 3, in reality it is difficult for the Read operation of the DDR SDRAM to meet the ‘tLZ’ specification, the data out impedance time from CLK, in data specifications for a systems company.
As explained above, the fact that the first data output is outputted early in the related art output buffer circuits leads to the difficulty in the satisfaction of the ‘tLZ’ specification, namely +/−700 ps. To solve this problem, namely to meet the ‘tLZ’ specification, trying to delay the output of the data output buffer for an arbitrary time toward the positive direction with reference to the external clock CLK leads to another difficulty in the satisfaction of the skew specification ‘tAC’, the data out access time from CLK, namely +/−700 ps.